Two mainstream metallization schemes for the deposition of copper currently exist for copper wiring or the provision of copper interconnects in semiconductor devices.
The dual damascene process is used for fine pitch metallization and is mainly used in logic and memory devices. In the dual damascene processes, a via may be etched, e.g. dry etched, beneath a patterned isolation layer such as silicon nitride. Copper may then be plated in the via. Chemical mechanical polishing (CMP) may then be used to clean the wafer surface from copper and to separate the copper lines from each other. Due to the costly reactive ion etching (RIE), copper plating and CMP processing, this metallization scheme is mainly used for signal wiring where low electric current allows thin layer processing.
Pattern plating of copper is conventionally used for applications requiring thick copper lines and electrically conductive bumps, such as copper bump arrays in wafer packaging. Copper may be plated using a resist mask which may be substantially thicker than the desired copper thickness. This metallization scheme is mainly used for high power devices where a high electric current has to be transported in the metal lines. Pattern copper plating is less expensive than the dual damascene metallization approach, however, the lithographic process to create a high standing mask and the plating process itself is very costly.
Once copper metallization has been carried out, patterning of a copper metallization layer may be carried out.
A first method of patterning a copper metallization layer is by carrying out a patterned copper etch. Patterned etching of a layer of copper may be carried out through a resist mask and using a copper wet etching chemistry, the wet etching chemistry being a chemical etchant. Although the patterned wet etch scheme is commonly used for structuring or etching other metals such as aluminum on a semiconductor wafer, it is not a feasible scheme to use for copper etching in the semiconductor industry because the copper etch process is highly influenced by the flow dynamics of the chemical etchant on the wafer.
The tools which are commercially available for wet processing or wet etching of metals, such as copper, offer a variety of different flow dynamics. One common tool for front end of line processing is the automated batch tank tool. Wafers that have structures to be etched may be immersed completely in a tank full of chemical etchant. The chemical etchant may be flowing homogenously through the tank from a diffuser located at the bottom of a tank. The etchant may be re-circulated using an overflow rinse. The flow dynamics of such a tool provides a very poor uniformity to the wafer etch due to the lack of control of flow dynamics.
Another common tool for carrying out a wet etch of a wafer surfaces to be etched is the a Spray Acid Tool (SAT). Wafers (in a batch 25-50) may be rotating within a process chamber while a chemical etchant is provided via spray nozzles above the wafer. The chemical etchant may be distributed over the surface of the wafer to be etched and is replaced by a combination of using a centrifugal force to provide rotation of the wafer and on the other hand by providing a new supply of chemical etchant provided by the spray nozzles. However, uniformity provided by the spray acid tool is highly dependent on the maximum flow of chemical etchant achievable.
As shown above both processes, the tank tool and the spray tool do not provide sufficient uniformity to be used as a direct metal (copper) structuring process suitable for the semiconductor industry.